Method and controller for processing data multiplication in raid system

ABSTRACT

The invention discloses a method and controller for processing data multiplication in a RAID system. Map tables are generated for all values in a field, respectively. The length of an XOR operation unit is chosen to be appropriate w bits (e.g., 32 bits or 64 bits). One or several XOR operation units form a multiplication unit of a data sector. When computing on-line, data in a disk drive of a disk array are performed with XOR operations in accordance with one of the map tables using an XOR operation unit as one unit while computing on the multiplication unit to obtain a product of multiplication. 
     Making use of the RAID system established according to the disclosed method, only XOR operations are required to compute parity data or recover damaged user data. Moreover, several calculations can be performed simultaneously. Therefore, the efficiency of the RAID system can be effectively improved.

CROSS REFERENCE TO RELATED APPLICATION(S)

This application is a Divisional application of U.S. patent applicationSer. No. 11/513,385, filed on Aug. 31, 2006, which claims the benefit ofprovisional Application No. 60/596,142, filed on Sep. 2, 2005, theentirety of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of Invention

The invention relates to a method and controller for processing datamultiplication in a RAID system and, in particular, to a method andcontroller for processing simultaneously a large amount of datamultiplication operations in a RAID system.

2. Related Art

The redundant array of independent disk (RAID) is a disk subsystemdesigned to enhance access efficiency, to provide better fault-toleranceability, or both. The RAID utilizes a disk striping technique to enhancethe access efficiency. Data are stored separately according to bytes orgroups of bytes in many different disk drives, so that the read/writeI/O requests can be performed in parallel on many disk drives. On theother hand, a mirroring technique or a disk striping technique withdistributive parity data is used to provide the fault-tolerance ability.

The ability of fault tolerance is related to the number of parity datasets stored in the RAID system. Taking RAID5 as an example, it isdesigned to store an extra set of parity data in addition to the userdata. The parity data is usually called the P value, or sometimes theXOR parity because it is the calculation result of XOR operations on thecorresponding user data. The formula is:

P=D ₀ +D ₁ +D ₂ + . . . +D _(n-1)  (1)

where + represents the XOR operation, P represents the parity dataseries, D₀, D₁, D₂, . . . , D_(n-1) represents the user data series,respectively, and n denotes the number of user data disks. As RAID5 onlystores one parity data set, it can only allow one of the user data diskshaving errors (e.g. damaged or out of order) at a time. The data on theuser data disk having errors is recovered using the corresponding Pvalue and the corresponding data on the other normal user data disks bymeans of the same XOR operations. For example, if D₁ has an error, thenD₁ can be recovered as follows:

D=D ₀ +D ₂ + . . . +D _(n-1) +P

-   -   where + also denotes the XOR operation.

Considering the fault tolerance demand on more than one user data disk,some systems are designed to store multiple parities. “Reed-SolomonCodes” are usually adopted to set up this type of RAID systems, whichallow more than one disk drive having errors. RAID6 belongs to thiscategory. It has at least two parities to allow two or more disk driveshaving errors at the same time.

Take the RAID6 system with two parities as an example. The two paritiesare conventionally called P and Q. The formula for computing P is thesame as the one in the RAID5 system. The value of Q is obtained usingthe following formula.

Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . +g ^(n-1) ·D _(n-1)  (2)

If two data disks D_(x), D_(y) are damaged, then a careful derivationgives:

D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy))  (3)

D _(y)=(P+P _(xy))+D _(x)  (4)

-   -   where A and B are constants only related to x and y:

A=g ^(y-x)·(g ^(y-x)+1)⁻¹  (5)

B=g ^(−x)·(g ^(y-x)+1)⁻¹  (6)

-   -   and P_(xy) and Q_(xy) are the values of P and Q when both D_(x)        and D_(y) are 0, i.e.,

P _(xy) +D _(x) +D _(y) =P  (7)

Q _(xy) ±g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q  (8)

Aside from the fact that the power “y−x” is a normal subtraction, theother algebraic operations in Eqs. (2) to (8) are all operationsfollowing the rules of the Galois Field. Moreover, g is a generator ofthe Galois Field. It usually be chosen as g=2.

The addition operation in the Galois Field is in fact the XOR operation.Its multiplication operation is related to the field of GF(2^(a)). Forthe definitions, properties, and operational rules, please refer to (1)“The mathematics of RAID6”, H. Peter Anvin, December, 2004; and (2) “ATutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-likeSystems”, James S. Plank, Software-Practice & Experience, 27(9), pp995-1012, September, 1997. Eqs. (1) to (8) given above can be found inRef. (1).

Since the Galois Field is a closed field and there always exists an rfor an arbitrary number X satisfying X=2^(r), in the prior art lookingup table is a typical method to deal with the multiplication operationsin the Galois Field (see Ref. (2)). Take GF(2^(a)) as an example. Tofind the product of any two numbers X and Y, the procedure is asfollows:

-   -   1. Look up a log table to find r and s, which satisfies X=2^(r)        and Y=2^(s). Therefore, X·Y=2^(r+s)=2^(t).    -   2. If t≧2^(a)−1, then t=t−(2^(a)−1).    -   3. Look up an inverse log table to obtain the value of 2^(t).

It is seen from Eqs. (2) and (3) that a large amount of multiplicationoperations of Galois Field are required for computing Q or recoveringthe damaged D. In particular, it involves the multiplication of aconstant with various different numbers. By means of the conventionalmethod of looking up table, the system has to compute byte by byte andeach multiplication operation of Galois Field requires 3 times of tablelooking up, 1 addition (or subtraction), 1 test and 1 modulo operation.Considering that the sizes of current storage media are frequently tensor hundreds of Giga bytes, such calculations are very inefficient andeasy to become the bottleneck of the system. Therefore, how to improveand/or simplify and/or speed up the data multiplication operations inthe RAID system is an important issue to be solved in the industry.

SUMMARY OF THE INVENTION

It is an objective of the invention to provide an effective algorithmand a controller implementing the algorithm, so that a huge amount ofdata multiplication operations can be performed simultaneously, therebyimproving the efficiency of a RAID system.

In accordance with one feature of the invention, a method for datamultiplication operations in a RAID system is provided. The methodincludes the steps of: generating at least one map table correspondingto at least one value in a field; selecting a length for an XORoperation unit and forming a multiplication unit using a plurality ofthe XOR operation units; and for the data stored in one disk drive ofthe RAID, performing at least one XOR operation using the XOR operationunit as one unit while computing on the multiplication unit according toa map table of the at least one map table, and further performing aplurality of the XOR operations to obtain the multiplication result.

In accordance with another feature of the invention, a controller forprocessing data multiplication operations in the RAID system isprovided. The controller includes: a memory for temporarily storingtarget data provided by a data source; and a central processing circuitthat generates at least one map table corresponding to at least onevalue in a field, performs at least one XOR operation for the targetdata stored in the memory using the XOR operation unit as one unit whilecomputing on the multiplication unit according to a map table of the atleast one map table, and further performs a plurality of the XORoperations to obtain the multiplication result.

In accordance with another feature of the invention, a method forprocessing data multiplication operations in a RAID system is provided,which is used to compute the product of a number K with a data series X.The method includes the steps of: generating a map table for the numberK; selecting a length of an XOR operation unit, and forming amultiplication unit using a plurality of the XOR operation units;dividing the data series X into at least one the multiplication unit;for the multiplication unit and the map table associated with the numberK, performing at least one XOR operation using the XOR operation unit asone unit according to the rules in the map table; and performing themultiplication operation in the previous step on all the multiplicationunits in the data series X. The multiplication result of the number Kwith the data series X is obtained once all the multiplicationoperations are done.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects and advantages of the invention willbecome apparent by reference to the following description andaccompanying drawings which are given by way of illustration only, andthus are not limitative of the invention, and wherein:

FIG. 1 is the primary flowchart of the invention;

FIG. 2 is a flowchart of generating map tables according to theinvention;

FIG. 3 is a schematic view of sampling data according to the invention;

FIG. 4 is a schematic view of sampling data in the prior art; and

FIG. 5 is a schematic view of an embodiment of the disclosed disksubsystem employing the method of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be apparent from the following detaileddescription, which proceeds with reference to the accompanying drawings,wherein the same references relate to the same elements.

A feature of the invention is in the appropriate definitions ofoperational rules for the data in the RAID system in order to speed upthe data operations. In practice, the operational rules for the RAIDdata are commonly taken to be the algebraic rules of the Galois Field.Therefore, the algebraic rules of the Galois Field are used in thefollowing embodiments. One embodiment of the invention is established onthe hypothesis of GF(2^(a)) of the Galois Field and its relatedalgebraic rules. As a=8 is a currently-preferred choice in practice,most of the embodiments in this specification assume the domain of theGalois Field to be GF(2⁸). That is, the covered numbers are between 0and 255. This is because 2⁸ is exactly the amount represented by onebyte which is a basic unit of computer memory. The RAID systemaccordingly established can accommodate up to 255 user data disks, whichare sufficient for normal RAID systems. Although the embodiments in thisspecification assume GF(2⁸), the invention can be applied to other caseswith other hypotheses. In other embodiments of the invention, thedisclosed technique may be applied in a Galois field domain differentfrom GF(2⁸). Moreover, the invention can also use the operations inother fields or number systems, as long as appropriate operational rulesare found in those fields or number systems.

Most of the embodiments described below take a RAID6 system with twoparities as the example. However, the invention can be applied to moregeneral cases. Other RAID 6 systems with more than two parities can beimplemented with the disclosed method as well. The conventional formulasquoted in the specification are listed as follows.

P=D ₀ +D ₁ +D ₂ + . . . +D _(n-1)  (1)

Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . +g ^(n-1) ·D _(n-1)  (2)

D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy))  (3)

D _(y)=(P+P _(xy))+D _(x)  (4)

A=g ^(y-x)·(g ^(y-x)+1)⁻¹  (5)

B=g ^(−x)·(g ^(y-x)+1)⁻¹  (6)

where P and Q are the two parities in the RAID6 system; x and y are theserial numbers of the two data disks with errors; D, and D_(y) are theuser data corresponding to the two data disks x and y; A and B areconstants only related to x and y; and P_(xy) and Q_(xy) are the valuesof P and Q when D_(x) and D_(y) are both 0, i.e.,

P _(xy) +D _(x) +D _(y) =P  (7)

Q _(xy) +g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q  (8)

Aside from the fact that the power “y−x” is a normal subtraction, theother algebraic operations in Eqs. (1) to (8) are all operationsfollowing the rules of the Galois Field. Moreover, g is a generator ofthe Galois Field. It usually be chosen as g=2.

Definition of the Map Table

The map table is a key ingredient of the invention. It is defined asfollows.

Suppose Y, X, and K are numbers in GF(2^(a)). That is, Y, X, and K areall composed of “a” bits. If y_(i) and x_(i) represents the i-th bits ofY and X, respectively, then the vectors Y and X can be represented by:

$\begin{matrix}{{Y = \begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\\vdots \\y_{a - 1}\end{bmatrix}},} & {X =}\end{matrix}\begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\\vdots \\x_{a - 1}\end{bmatrix}$

Let Y=K·X; that is, Y is the multiplication result of K with anarbitrary number X in the Galois Field. Here K is a given constant. Thenthe map table of K is defined as an a×a matrix M_(K), whose elementsm_(i,j) (0<=i, j<=a−1) are 0 or 1 and satisfy:

$\begin{matrix}{Y = {\begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\\vdots \\y_{a - 1}\end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix}m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,{a - 1}} \\m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,{a - 1}} \\m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,{a - 1}} \\\vdots & \vdots & \vdots & \vdots & \vdots \\m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},{a - 1}}\end{bmatrix} \cdot \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\\vdots \\x_{a - 1}\end{bmatrix}}}}} & (9)\end{matrix}$

In other words,

$\begin{matrix}{{{y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{i,j} \cdot x_{j}} \right)}},{{{wherein}\mspace{14mu} 0} \leqq i \leqq {a - 1}}}{where}{{{m_{i,j} \cdot x_{j}} = x_{j}},{{{{if}\mspace{14mu} m_{i,j}} = 1};}}{{{m_{i,j} \cdot x_{j}} = 0},{{{if}\mspace{14mu} m_{i,j}} = 0.}}} & (10)\end{matrix}$

The addition in the above operations is defined as the XOR operation.Since the elements in the matrix M_(K) are either 0 or 1, thecomputation of y, can be regarded as follows: the data units x_(j)corresponding to m_(i,j)=1 in the i-th row of the matrix M_(K) areselected to do XOR operations.

Generation of the Map Table

The way of generating the map table is closely related to the algebraicrules of the Galois Field. Take GF(2⁸) as an example. Suppose theproduct of an arbitrary number X and 2 is X□′, then X□′ can be obtainedfrom the following formula (“+” represents an XOR operation):

${{X\; \bullet^{\prime}} = {\begin{bmatrix}x_{0}^{\prime} \\x_{1}^{\prime} \\x_{2}^{\prime} \\x_{3}^{\prime} \\x_{4}^{\prime} \\x_{5}^{\prime} \\x_{6}^{\prime} \\x_{7}^{\prime}\end{bmatrix} = \begin{bmatrix}x_{7} \\x_{0} \\{x_{1} + x_{7}} \\{x_{2} + x_{7}} \\{x_{3} + x_{7}} \\x_{4} \\x_{5} \\x_{6}\end{bmatrix}}};{{{where}\mspace{14mu} X} = \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\x_{3} \\x_{4} \\x_{5} \\x_{6} \\x_{7}\end{bmatrix}}$

Suppose the map table of K is a given matrix M_(K) and the map table ofK′=2·K is the matrix M_(K′). Based on the above formula, one can derivethe algorithmic rule A for generating M_(K′) from M_(K), shown in Table1:

TABLE 1 m′_(0,j) = m_(7,j) , 0 <= j <= 7 m′_(1,j) = m_(0,j) , 0 <= j <=7 m′_(2,j) = m_(1,j) + m_(7,j) , 0 <= j <= 7 m′_(3,j) = m_(2,j) +m_(7,j) , 0 <= j <= 7 m′_(4,j) = m_(3,j) + m_(7,j) , 0 <= j <= 7m′_(5,j) = m_(4,j) , 0 <= j <= 7 m′_(6,j) = m_(5,j) , 0 <= j <= 7m′_(7,j) = m_(6,j) , 0 <= j <= 7

One algebraic feature of the Galois Field is as follows. Start from K=1and multiply K each time by 2. The derived new K values do not repeatuntil covering all the numbers in the Galois Field. Take GF(2⁸) as anexample. Start from K=1 and record it. Multiply K by 2 each time. After255 times recording, the derived K values will cover all the GF(2⁸)numbers (except for 0).

According to the above-mentioned algebraic properties of the GaloisField and the algorithmic rule A, all map tables corresponding todifferent K values, i.e., all the matrix M_(K), can be generated. Pleaserefer to FIG. 1. According to an embodiment of the invention, generatingthe map tables (step 200) is the first key step of the invention and itsimplementation is described as follows.

With reference to FIG. 2, while beginning to generate the map tables(step 201), the algorithmic rule A for generating the matrix M_(K′) fromthe matrix M_(K) should be determined first according to the selectedGalois Field GF(2^(a)) and its algebraic rules (step 202), where M_(K)denotes the map table of a constant K and M_(K′) denotes the map tableof 2·K. When K=0, its map table is defined to be the zero matrix (step203). When K=1, its map table is defined to be the identity matrix (step204). The map tables thus generated are stored in the system memory. TheK value whose map table is already produced is marked as “completed”(step 205). Afterwards, K starts from K=1 and is multiplied each time by2 (step 206). The system checks whether the K value is marked as“completed” (step 207). If so, then the procedure is finished (step209); otherwise, the map table M_(K) of the new K value is generatedaccording to the algorithmic rule A (step 208). The procedure thenreturns to step 205, marking K as “completed” and generating the nextnew K value (step 206), and so on. Steps 205˜208 are repeated until Kvalue is repeated and then the procedure is finished (step 209).

A few map tables in GF(2⁸) are listed below for references.

$\begin{matrix}{K = 0} & {K = {2^{0} = 1}} \\{M_{0} = \begin{bmatrix}0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 0\end{bmatrix}} & {M_{1} = \begin{bmatrix}1 & 0 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 1 & 0 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 0 & 0 & 1\end{bmatrix}} \\{K = {2^{27} = 12}} & {K = {2^{55} = 160}} \\{M_{12} = \begin{bmatrix}1 & 1 & 1 & 0 & 0 & 0 & 1 & 0 \\0 & 1 & 1 & 1 & 0 & 0 & 0 & 1 \\1 & 1 & 0 & 1 & 1 & 0 & 1 & 0 \\1 & 0 & 0 & 0 & 1 & 1 & 1 & 1 \\0 & 0 & 1 & 0 & 0 & 1 & 0 & 1 \\0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\1 & 1 & 0 & 0 & 0 & 1 & 0 & 0\end{bmatrix}} & {M_{160} = \begin{bmatrix}0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\0 & 0 & 0 & 1 & 0 & 1 & 0 & 1 \\0 & 0 & 1 & 0 & 0 & 0 & 0 & 1 \\0 & 0 & 1 & 1 & 1 & 0 & 1 & 1 \\1 & 0 & 1 & 1 & 0 & 1 & 1 & 0 \\0 & 1 & 0 & 1 & 1 & 0 & 1 & 1 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0\end{bmatrix}}\end{matrix}$

Application of the Map Table

One advantage of using the map tables for the multiplication operationsin the Galois Field is to avoid the operations of shifting digits orlooking up the log table/inverse log table. All it needs is the XORoperations.

Take GF(2⁸) as an example. Suppose Y is the product of a constant 20 andan arbitrary number X, i.e., Y=20 X, and the map table associated with20 (the matrix M₂₀) is given as:

$\begin{matrix}{M_{20} = \begin{bmatrix}0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\0 & 0 & 0 & 1 & 0 & 1 & 0 & 1\end{bmatrix}} & (11)\end{matrix}$

According to the definition,

$\begin{matrix}{Y = {\begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\y_{3} \\y_{4} \\y_{5} \\y_{6} \\y_{7}\end{bmatrix} = {{\begin{bmatrix}0 & 0 & 0 & 0 & 1 & 0 & 1 & 0 \\0 & 0 & 0 & 0 & 0 & 1 & 0 & 1 \\1 & 0 & 0 & 0 & 1 & 0 & 0 & 0 \\0 & 1 & 0 & 0 & 1 & 1 & 1 & 0 \\1 & 0 & 1 & 0 & 1 & 1 & 0 & 1 \\0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\0 & 0 & 1 & 0 & 1 & 0 & 1 & 1 \\0 & 0 & 0 & 1 & 0 & 1 & 0 & 1\end{bmatrix} \cdot \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\x_{3} \\x_{4} \\x_{5} \\x_{6} \\x_{7}\end{bmatrix}} = {\quad\begin{bmatrix}{x_{4} + x_{6}} \\{x_{5} + x_{7}} \\{x_{0} + x_{4}} \\{x_{1} + x_{4} + x_{5} + x_{6}} \\{x_{0} + x_{2} + x_{4} + x_{5} + x_{7}} \\{x_{1} + x_{3} + x_{5} + x_{6}} \\{x_{2} + x_{4} + x_{6} + x_{7}} \\{x_{3} + x_{5} + x_{7}}\end{bmatrix}}}}} & (12)\end{matrix}$

For example, if X=83, then Y=8, as given below:

${\begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\x_{3} \\x_{4} \\x_{5} \\x_{6} \\x_{7}\end{bmatrix} = \begin{bmatrix}1 \\1 \\0 \\0 \\1 \\0 \\1 \\0\end{bmatrix}},{\begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\y_{3} \\y_{4} \\y_{5} \\y_{6} \\y_{7}\end{bmatrix} = {\begin{bmatrix}{x_{4} + x_{6}} \\{x_{5} + x_{7}} \\{x_{0} + x_{4}} \\{x_{1} + x_{4} + x_{5} + x_{6}} \\{x_{0} + x_{2} + x_{4} + x_{5} + x_{7}} \\{x_{1} + x_{3} + x_{5} + x_{6}} \\{x_{2} + x_{4} + x_{6} + x_{7}} \\{x_{3} + x_{5} + x_{7}}\end{bmatrix} = {\begin{bmatrix}{1 + 1} \\{0 + 0} \\{1 + 1} \\{1 + 1 + 0 + 1} \\{1 + 0 + 1 + 0 + 0} \\{1 + 0 + 0 + 1} \\{0 + 1 + 1 + 0} \\{0 + 0 + 0}\end{bmatrix} = \begin{bmatrix}0 \\0 \\0 \\1 \\0 \\0 \\0 \\0\end{bmatrix}}}}$

If the value of Y is computed using the conventional technique bylooking up the log table/inverse log table, then

Y=20·83=2²⁰⁶·2⁵²=2²⁰⁶⁺⁵²=2²⁵⁸=2²⁵⁸⁻²⁵⁵=2³=8

which is the same as the result computed by the disclosed technique ofthe invention.

Explanation of the Algorithm

The disclosed algorithm of the invention allows the operations of a hugeamount of Galois Field multiplication to proceed at the same time,particularly the multiplication operations of a constant with a lot ofdifferent numbers. Therefore, it speeds up the operations in a RAIDsystem.

Please refer to FIG. 1. According to one embodiment of the invention,the disclosed method includes three steps. First, the domain ofGF(2^(a)) of the Galois Field is determined. The map tables of allvalues in GF(2^(a)) are produced according to the algebraic rules of theGalois Field and stored in the memory (step 200). Secondly, the XORoperation unit is enlarged to appropriate w bits. Therefore, themultiplication unit is enlarged to be w a bits (step 300). Thirdly,according to the stored map tables and its operational rules, each datasector of w bits in the multiplication unit are selected as an XORoperation unit for the XOR operation when the system computes themultiplication of the Galois Field on-line (step 400). Wherein, the maptables mentioned in the first step can be generated in real time whileprocessing data operations, instead of being all generated right afterthe system is turned on. However, if all the map tables can be generatedright after the system is power on, it will be more convenient forsubsequent operations. On the other hand, if the required map tables aretoo many and not suitable for production and storage at a time, thenreal-time generation during the operation is another feasible option.

How to generate the map tables (step 200) is already described above.

The technique of how to enlarge the XOR operation unit to w bits (step300) is described as follows.

According to the definition of the map table, i.e. Eq. (9), y_(i) andx_(i) denote the i-th bit of Y and X, respectively, where Y and X arenumbers in GF(2^(a)). It implies that when the map tables are used forconventional operations, the XOR operation unit is 1 bit and themultiplication unit is a number in GF(2^(a)). The disclosed method ofthe invention enlarges the XOR operation unit to w bits, and thus themultiplication unit is enlarged to w a bits. Take GF(2⁸) as an example.If setting w=32, then the XOR operation unit has 32 bits according tothe invention, and the multiplication unit has 32·8=256 bits=32 bytes,namely, the set of 32 numbers in GF(2⁸).

One of the chief considerations of selecting the length of the XORoperation unit to be w is the system hardware environment. For example,the consideration could be the operation unit of the CPU or dedicatedXOR operation unit or the width of the data bus. If the operation unitof the CPU or dedicated XOR operation unit is 32 bits, then w=32 is anappropriate choice. If the operation unit of the CPU or dedicated XORoperation unit is 64 bits, then setting w=64 is suitable. Of course, itdoes not imply that the choice of w is necessarily limited to be thesame as the length of the operation unit of the CPU or dedicated XORoperation unit. Different w values may be used in other embodiments ofthe invention.

Another factor influencing the value of w is considering that the basicstorage unit (a sector) of the disks had better be an integer multipleof the multiplication unit. Take GF(2⁸) as an example. If setting w=20,then the multiplication unit has 20 8=160 bits=20 bytes. The basicstorage unit, i.e. a sector, of the disks usually has 512 bytes. Since512 is not an integer multiple of 20, therefore additional operationshave to be performed when the multiplication unit is incomplete.

After determining the value of w, the system can perform onlinemultiplication of the Galois Field according to the map tables (step400). The multiplication may be performed for computing a parity or lostuser data. The operation rule is still following Eq. (9). However, theXOR operation unit is enlarged to an appropriate w bits, and themultiplication unit is enlarged to w·a bits. That is, both y_(i) andx_(i) have w bits, and both Y and X have w·a bits.

In the following, an embodiment is used to explain the disclosed method.If it is the intention to calculate the product of Y=20·X in GF(2⁸). Xis a 32-byte data sector. In the hexadecimal number system, X isrepresented as follows:

$X = \begin{matrix}\left| \overset{B_{0}}{25\mspace{14mu} 2a\mspace{14mu} 1b\mspace{14mu} 33} \middle| \overset{B_{4}}{52\mspace{14mu} 6a\mspace{14mu} 11\mspace{14mu} 90} \middle| \overset{B_{8}}{80\mspace{14mu} 46\mspace{14mu} 7c\mspace{14mu} a\; b} \middle| \overset{B_{12}}{6e\mspace{14mu} 21\mspace{14mu} 5b\mspace{14mu} 44} \right| \\\left| \overset{B_{16}}{a\; 5\mspace{14mu} 42\mspace{14mu} 78\mspace{14mu} 03} \middle| \overset{B_{20}}{77\mspace{14mu} 25\mspace{14mu} 19\mspace{14mu} 64} \middle| \overset{B_{24}}{01\mspace{14mu} 92\mspace{14mu} 47\mspace{14mu} 86} \middle| \overset{B_{28}}{22\mspace{14mu} 55\mspace{14mu} 9a\mspace{14mu} 76} \right|\end{matrix}$

where the 0-th byte of X is denoted by B₀, the first byte by B₁, thesecond byte by B₂, and so on, until B₃₁.

According to the disclosed method, the RAID system computes and storesall the map tables when its starts. Therefore, the map table associatedwith 20 is already given. Suppose the system CPU is 32-bit. Therefore, wis set to be 32. In this case, Y and X are considered to be the dataseries composed of 8 units, given as:

-   -   Y=y₀ y₁ y₂ y₃ y₄ y₅ y₆ y₇    -   X=x₀ x₁ x₂ x₃ x₄ x₅ x₆ x₇        where y_(i) and x_(i) represent operation units consisting of 32        bits (4 bytes), 0≦i≦7.

${{Set}\mspace{14mu} X} = \begin{matrix}\left| \overset{x_{0}}{25\mspace{14mu} 2a\mspace{14mu} 1b\mspace{14mu} 33} \middle| \overset{x_{1}}{52\mspace{14mu} 6a\mspace{14mu} 11\mspace{14mu} 90} \middle| \overset{x_{2}}{80\mspace{14mu} 46\mspace{14mu} 7c\mspace{14mu} a\; b} \middle| \overset{x_{3}}{6e\mspace{14mu} 21\mspace{14mu} 5b\mspace{14mu} 44} \right| \\\left| \overset{x_{4}}{a\; 5\mspace{14mu} 42\mspace{14mu} 78\mspace{14mu} 03} \middle| \overset{x_{5}}{77\mspace{14mu} 25\mspace{14mu} 19\mspace{14mu} 64} \middle| \overset{x_{6}}{01\mspace{14mu} 92\mspace{14mu} 47\mspace{14mu} 86} \middle| \overset{x_{7}}{22\mspace{14mu} 55\mspace{14mu} 9a\mspace{14mu} 76} \right|\end{matrix}$

The map table of the constant 20 is already given in Eq. (11). UsingEqs. (9) and (12), one obtains (in the hexadecimal system):

y ₀ =x ₄ +x ₆=(a5 42 78 03)+(01 92 47 86)=(a4 d0 3f 85)

y ₁ =x ₅ +x ₇=(77 25 19 64)+(22 55 9a 76)=(55 70 83 12)

y ₂ =x ₀ +x ₄=(25 2a 1b 33)+(a5 42 78 03)=(80 68 63 30)

y ₃ =x ₁ +x ₄ +x ₅ +x ₆=(52 6a 11 90)+(a5 42 78 03)+(77 25 19 64)+(01 9247 86)=(81 9f 37 71)

y ₄ =x ₀ +x ₂ +x ₄ +x ₅ +x ₇=(25 2a 1b 33)+(80 46 7c ab)+(a5 42 7803)+(77 25 19 64)+(01 92 47 86)=(55 5e 9c 89)

y ₅ +x ₃ +x ₅ +x ₆=(52 6a 11 90)+(6e 21 5b 44)+(77 25 19 64)+(01 92 4786)=(4a fc 14 36)

y ₆ =x2+x ₄ +x ₆ +x ₇=(80 46 7c ab)+(a5 42 78 03)+(01 92 47 86)+(22 559a 76)=(06 c3 d9 58)

y ₇ =x ₃ +x ₅ +x ₇=(6e 21 5b 44)+(77 25 19 64)+(22 55 9a 76)=(3b 51 d856)

Therefore, Y=|a4 d0 3f 85|55 70 83 12|80 68 63 30|81 9f 37 71∥55 5e 9c89|4a fc 14 36|06 c3 d9 58|3b 51 d8 56|

The above example assumes that the length of X is 32 bytes. If thelength of X is greater than 32 bytes, then X is divided into groups eachcomposed of 32 bytes. Each group of 32 byte forms a multiplication unit.Therefore, the product Y can be obtained by repeating the aboveoperations.

Features of the Algorithm

Using the disclosed algorithm of the invention on the RAID system, theobtained parity is different from that obtained in the prior art.However, its effect and the way of application are completely the sameas the prior art.

For example, suppose D₀, D₁, and D₂ are three disk drives for storinguser data, which are 32-byte data series, shown as follows (expressed inthe hexadecimal system):

$D_{0} = \begin{matrix}\left| \overset{B_{0}}{2a\mspace{14mu} 16\mspace{14mu} 10\mspace{14mu} 36} \middle| \overset{B_{4}}{50\mspace{14mu} 14\mspace{14mu} 18\mspace{14mu} 66} \middle| \overset{B_{8}}{5\; c\mspace{14mu} 01\mspace{14mu} 06\mspace{14mu} 12} \middle| \overset{B_{12}}{35\mspace{14mu} 7\; e\mspace{14mu} 46\mspace{14mu} 0\; a} \right| \\\left| \overset{B_{16}}{1a\mspace{20mu} 39\mspace{14mu} 6f\mspace{14mu} 17} \middle| \overset{B_{20}}{59\mspace{14mu} 75\mspace{14mu} 48\mspace{14mu} 5d} \middle| \overset{B_{24}}{2a\mspace{14mu} 07\mspace{14mu} 57\mspace{14mu} 39} \middle| \overset{B_{28}}{0f\mspace{14mu} 30\mspace{14mu} 21\mspace{14mu} 30} \right|\end{matrix}$ $D_{1} = \begin{matrix}\left| \overset{B_{0}}{19\mspace{14mu} 38\mspace{14mu} 25\mspace{14mu} 26} \middle| \overset{B_{4}}{0c\mspace{14mu} 49\mspace{14mu} 57\mspace{14mu} 51} \middle| \overset{B_{8}}{6a\mspace{14mu} 35\mspace{14mu} 27\mspace{14mu} 65} \middle| \overset{B_{12}}{23\mspace{14mu} 09\mspace{14mu} 62\mspace{14mu} 28} \right| \\\left| \overset{B_{16}}{58\mspace{14mu} 7f\mspace{14mu} 5d\mspace{14mu} 7e} \middle| \overset{B_{20}}{12\mspace{14mu} 15\mspace{14mu} 5d\mspace{14mu} 7a} \middle| \overset{B_{24}}{3d\mspace{14mu} 48\mspace{14mu} 4c\mspace{14mu} 6b} \middle| \overset{B_{28}}{5b\mspace{14mu} 40\mspace{14mu} 74\mspace{14mu} 4c} \right|\end{matrix}$ $D_{2} = \begin{matrix}\left| \overset{B_{0}}{7c\mspace{14mu} 1c\mspace{14mu} 5d\mspace{14mu} 22} \middle| \overset{B_{4}}{3d\mspace{14mu} 61\mspace{14mu} 7d\mspace{14mu} 3c} \middle| \overset{B_{8}}{75\mspace{14mu} 2b\mspace{14mu} 3e\mspace{14mu} 70} \middle| \overset{B_{12}}{14\mspace{14mu} 4e\mspace{14mu} 42\mspace{14mu} 18} \right| \\\left| \overset{B_{16}}{6d\mspace{14mu} 0d\mspace{14mu} 6e\mspace{14mu} 05} \middle| \overset{B_{20}}{31\mspace{14mu} 55\mspace{14mu} 78\mspace{14mu} 47} \middle| \overset{B_{24}}{3b\mspace{14mu} 72\mspace{14mu} 67\mspace{14mu} 70} \middle| \overset{B_{28}}{1f\mspace{14mu} 0b\mspace{14mu} 14\mspace{14mu} 3e} \right|\end{matrix}$

where B₀ denotes the 0-th byte, B₁ the first byte, and so on, until B₃₁.The RAID6 system comprising the three user data disk drives requiresadditional two party data disk drives for storing parities P and Q.According to Eqs. (1) and (2), one obtains:

P=D ₀ +D ₁ +D ₂

Q=2⁰ ·D ₀+2¹ ·D ₁+2² ·D ₂

In the prior art, the values of P and Q in GF(2⁸) are computed asfollows:

$P = \begin{matrix}\left| \overset{B_{0}}{4f\mspace{14mu} 32\mspace{14mu} 68\mspace{14mu} 32} \middle| \overset{B_{4}}{61\mspace{14mu} 3c\mspace{14mu} 32\mspace{14mu} 0b} \middle| \overset{B_{8}}{43\mspace{14mu} 1f\mspace{14mu} 1f\mspace{14mu} 07} \middle| \overset{B_{12}}{02\mspace{14mu} 39\mspace{14mu} 66\mspace{14mu} 3a} \right| \\\left| \overset{B_{16}}{2f\mspace{14mu} 4b\mspace{14mu} 5c\mspace{14mu} 6c} \middle| \overset{B_{20}}{7a\mspace{14mu} 35\mspace{14mu} 6d\mspace{14mu} 60} \middle| \overset{B_{24}}{2c\mspace{14mu} 3d\mspace{14mu} 7c\mspace{14mu} 22} \middle| \overset{B_{28}}{4b\mspace{14mu} 7b\mspace{14mu} 41\mspace{14mu} 42} \right|\end{matrix}$ $Q = \begin{matrix}\left| \overset{B_{0}}{f\; 5\mspace{14mu} 16\mspace{14mu} 33\mspace{14mu} f\; 2} \middle| \overset{B_{4}}{{bc}\mspace{14mu} 1f\mspace{14mu} 5f\mspace{14mu} 34} \middle| \overset{B_{8}}{41\mspace{14mu} c\; 7\mspace{14mu} b\; 0\mspace{14mu} 05} \middle| \overset{B_{12}}{23\mspace{14mu} 49\mspace{14mu} 97\mspace{14mu} 3a} \right| \\\left| \overset{B_{16}}{03\mspace{14mu} f\; 3\mspace{14mu} 70\mspace{14mu} {ff}} \middle| \overset{B_{20}}{b\; 9\mspace{14mu} 16\mspace{14mu} 0f\mspace{14mu} a\; 8} \middle| \overset{B_{24}}{{bc}\mspace{14mu} 42\mspace{14mu} 4e\mspace{14mu} 32} \middle| \overset{B_{28}}{c\; 5\mspace{14mu} 9c\mspace{14mu} 99\mspace{14mu} 50} \right|\end{matrix}$

Using the disclosed method of the invention, the P value is unchanged.The value of Q is as follows (assuming w=32):

$Q = \begin{matrix}\left| \overset{B_{0}}{4a\mspace{14mu} 24\mspace{14mu} 03\mspace{14mu} 0a} \middle| \overset{B_{4}}{56\mspace{14mu} 27\mspace{14mu} 29\mspace{14mu} 7e} \middle| \overset{B_{8}}{4c\mspace{14mu} 66\mspace{14mu} 1f\mspace{14mu} 5d} \middle| \overset{B_{12}}{1d\mspace{14mu} 13\mspace{14mu} 1b\mspace{14mu} 51} \right| \\\left| \overset{B_{16}}{33\mspace{14mu} 22\mspace{14mu} 34\mspace{14mu} 4d} \middle| \overset{B_{20}}{0a\mspace{14mu} 4f\mspace{14mu} 43\mspace{14mu} 05} \middle| \overset{B_{24}}{55\mspace{14mu} 1f\mspace{14mu} 64\mspace{14mu} 46} \middle| \overset{B_{28}}{03\mspace{14mu} 2d\mspace{14mu} 15\mspace{14mu} 1c} \right|\end{matrix}$

Suppose the data in D₀ and D₂ are damaged, they can be recovered byusing D₁, P, and Q. Using Eqs. (3), (4), (5), (6), (7), and (8), oneobtains:

x=0, y=2, A=166, B=167;

D ₀=166·P+167·Q+245·D ₁

D ₂ =P+D ₁ +D ₀  (13)

1. In the prior art, each byte is computed one by one to solve:

166·P=|fe 9a d2 9a|2d 30 9a ae|05 be be 55|51 34 78 c3∥75 5c bb 70|31 cfd6 8b|82 96 c2 28|5c 97 54 a3

167·Q=|31 57 0f 63|75 a1 13 5d|15 99 82 01|ad 44 89 f9∥f4 c4 49 33|74 5703 71|75 e1 16a 8|ca 2c 2d 10|

245·D ₁ =|e5 db cd cf|08 85 91 95|4c 26 3a 46|c9 0e b7 30∥9b a1 9d 54|1ced 9d a7|dd 70 83 b9|99 8b 58 83|

Therefore,

D ₀=|2a 16 10 36|50 14 18 66|5c 01 06 12|35 7e 46 0a∥1a 39 6f 17|59 7548 5d|2a 07 57 39|0f 30 21 30|

D₂ is then obtained by substituting D₀ in Eq. (13).

2. According to the disclosed method of the invention, one obtains:

166·P=|52 4b 78 13|0f 5b 57 7b|4f 32 68 32|33 77 4a 18∥51 3d 58 5d|3e 157b 59|7e 76 04 31|44 20 16 39|

167·Q=|08 72 67 3c|36 58 65 22|06 42 1c 57|09 62 56 19∥17 49 00 70|63 5259 40|42 56 64 36|60 7f 4c 5c|

245·D ₁=|70 2f 0f 19|69 17 2a 3f|15 71 72 77|0f 6b 5a 0b∥5c 4d 37 3a|0432 6a 44|16 27 37 3e|2b 6f 7b 55|

Therefore,

D ₀=|2a 16 10 36|50 14 18 66|5c 01 06 12|35 7e 46 0a∥1a 39 6f 17|59 7548 5d|2a 07 57 39|0f 30 21 30|

Likewise, D₂ is obtained by substituting D₀ in Eq. (13).

The above example reveals that even though the value of Q obtained bythe techniques disclosed in the invention is different from the onecomputed by the prior art, however, the functions of protecting andrecovering the user data are identical to the one in the prior art.

Correctness of the Algorithm and its Mathematical Meaning

Take GF(2⁸) as an example. Suppose Y and X are composed of 8 XORoperation units, each of which has a length of w bits. Here w is anappropriate number, such as 32 in the previous example. Y and X arerepresented in a vector format as follows,

${Y = \begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\\vdots \\y_{7}\end{bmatrix}},{X = \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\\vdots \\x_{7}\end{bmatrix}}$

where y_(i) and x_(i) are w-bit numbers and 0≦i≦7.

Let Y=K·X, where K is a constant whose map table is the matrix M_(K).Then

${y_{i} = {\sum\limits_{j = 0}^{7}\left( {m_{ij} \cdot x_{j}} \right)}},{{{wherein}\mspace{14mu} 0} \leqq i \leqq 7}$

That is,

$y_{0} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j}} \right)}$$y_{1} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j}} \right)}$$y_{2} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j}} \right)}$$y_{3} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j}} \right)}$$y_{4} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j}} \right)}$$y_{5} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j}} \right)}$$y_{6} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j}} \right)}$$y_{7} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j}} \right)}$

Let y_(i,j) and x_(i,j) denote the j-th bits of y_(i) and x_(i),respectively, where 0≦i≦7 and 0≦j≦w−1. Since both y_(i) and x_(i) have wbits, the above equations can be unfolded as follows:

$\begin{matrix}{{y_{0,0} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,0}} \right)}}{{y_{0,1} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{0,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{0,j} \cdot x_{j,{w - 1}}} \right)}}} & (14) \\{{y_{1,0} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,0}} \right)}}{{y_{1,1} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{1,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{1,j} \cdot x_{j,{w - 1}}} \right)}}} & (15) \\{{y_{2,0} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,0}} \right)}}{{y_{2,1} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{2,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{2,j} \cdot x_{j,{w - 1}}} \right)}}} & (16) \\{{y_{3,0} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,0}} \right)}}{{y_{3,1} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{3,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{3,j} \cdot x_{j,{w - 1}}} \right)}}} & (17) \\{{y_{4,0} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,0}} \right)}}{{y_{4,1} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{4,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{4,j} \cdot x_{j,{w - 1}}} \right)}}} & (18) \\{{y_{5,0} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,0}} \right)}}{{y_{5,1} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{5,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{5,j} \cdot x_{j,{w - 1}}} \right)}}} & (19) \\{{y_{6,0} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,0}} \right)}}{{y_{6,1} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{6,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{6,j} \cdot x_{j,{w - 1}}} \right)}}} & (20) \\{{y_{7,0} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,0}} \right)}}{{y_{7,1} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,1}} \right)}},\ldots}{{{and}\mspace{14mu} {so}\mspace{14mu} {forth}\mspace{14mu} {until}\mspace{14mu} y_{7,{w - 1}}} = {\sum\limits_{j = 0}^{7}\left( {m_{7,j} \cdot x_{j,{w - 1}}} \right)}}} & (21)\end{matrix}$

Analyzing Eqs. (14) to (21), one finds:

$\begin{bmatrix}y_{0,0} \\y_{1,0} \\y_{2,0} \\\vdots \\y_{7,0}\end{bmatrix} = {\begin{bmatrix}m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,7} \\m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,7} \\m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,7} \\\vdots & \vdots & \vdots & \; & \vdots \\m_{7,0} & m_{7,1} & m_{7,2} & \ldots & m_{7,7}\end{bmatrix}_{K} \cdot \begin{bmatrix}x_{0,0} \\x_{1,0} \\x_{2,0} \\\vdots \\x_{7,0}\end{bmatrix}}$

That is, (y_(0,0) y_(1,0) . . . y_(7,0)) and (x_(0,0) x_(1,0) . . .x_(7,0)) satisfy the definition of the map table in Eq. (9). Therefore,the former one is the product of K and the latter one in the GaloisField. Likewise, the numbers of (y_(0,j) y_(1,j) . . . y_(7,j)) for allj satisfying 0≦j≦w−1 are the products of K and (x_(0,j) x_(1,j) . . .x_(7,1)).

The above-mentioned analysis provides a mathematical meaning for thedisclosed technique. Please refer to FIG. 3 and take GF(2⁸) as anexample. The Galois Field products obtained according to the inventionis equivalent to the results obtained from the following steps:

-   -   1. Read the data sector with a length of (w·8) bits, where w is        an appropriate value as described above.    -   2. In the data sector, start from the i-th bit and pick one bit        every w bits, until it forms a GF(2⁸) number x_(i), wherein        0≦i≦7.    -   3. Obtain ∩y_(i)=K˜x_(i), wherein 0≦i≦7, using the conventional        techniques.    -   4. Store y_(i) back to the memory address where stores the final        multiplication product. The location of each bit of y_(i) should        move back to the one corresponding to the original location in        x_(i), wherein 0≦i≦7.

From the viewpoint of the “equivalent method” mentioned above, thedisclosed method of the invention still follows the algebraic principlesof the Galois Field. The difference from the prior art is the way ofdata sampling. That is, the disclosed method of the invention can beregarded as being equivalent to sampling one bit every w bits in thedata sector until a GF(2^(a)) number is obtained.

For example, as shown in FIG. 3, suppose an XOR operation unit has wbits of a data length, and 8 XOR operation units form a multiplicationunit. One embodiment of the invention is considered to be equivalent tothe multiplication result outlined in the following steps. Step1, pickthe first bit of each XOR operation unit to form an 8-bit number(b₀b₁b₂b₃b₄b₅b₆b₇). Multiply K by (b₀b₁b₂b₃b₄b₅b₆b₇) to obtain(b₀′b₁′b₂′b₃′b₄b₅′b₆′b₇′). Then, put each bit of(b₀′b₁′b₂′b₃′b₄′b₅′b₆′b₇′) back to the corresponding location where theoriginal (b₀b₁b₂b₃b₄b₅b₆b₇) comes from. Step2, perform the operationwith the same K on the number (c₀c₁c₂c₃c₄c₅c₆c₇) formed by picking thesecond bit of each XOR operation unit and then obtain(c₀′c₁′c₂′c₃′c₄′c₅′c₆′c₇′). Put each bit of (c₀′c₁′c₂′c₃′c₄′c₅′c₆′c₇′)back to the corresponding location where the original (c₀c₁c₂c₃c₄c₅c₆c₇)comes from. This procedure repeats until all the w·8 bits are computed.

In contrast, the prior art samples data in sequence, as shown in FIG. 4.The product of each byte with K has to be computed one by one.Therefore, it is difficult to enlarge the data amount computed so as tospeed up the operation.

From the equivalent point of view mentioned above, although theinvention has different sampling method from the prior art, this doesnot affect the correctness of Eqs. (2) to (8). Therefore, the functionsof data protecting and recovering remain the same.

The above-mentioned “equivalent method” is only for explaining theessence of the invention. In practice, the disclosed method of theinvention can simultaneously compute several Galois Field products,thereby increasing the operation speed of the RAID system. Thisadvantage originates from the special data sampling method in the“equivalent method”.

System Structure Using the Disclosed Algorithm

In an embodiment of the invention, the disclosed method is applied to aredundant array of independent disk (RAID) subsystem. With reference toFIG. 5, the physical storage device (PSD) array 600 consists of severaldisk drives. When a host 10 accesses the PSD array 600, the entire PSDarray 600 is regarded as a single logic disk drive. The primaryobjective of a storage virtualization controller (SVC) 100 is to map thecombination of all sectors in the disk drives to form a logic disk drivevisible to the host 10. After an I/O request sent out from the host 10is received by the controller 100, the I/O request is first analyzed andinterpreted. The related operations and data are then compiled into I/Orequests of the disk drives.

In this embodiment, the SVC 100 comprises a host-side I/O deviceinterconnect controller 120, a central processing circuit (CPC) 140, amemory 180, and a device-side I/O device interconnect controller 500.Although these components are described using individual functionalblocks, in practice some or even all the functional blocks can beintegrated on a single chip.

The host-side I/O device interconnect controller 120 is connected to thehost 10 and the CPC 140 to be the interface and buffer between the SVC100 and the host 10. It receives the I/O requests and the related datatransmitted from the host 10 and converts and/or maps them to the CPC140.

The memory 180 is connected to the CPC 140 to be a buffer. It buffersthe data transmitted between the host 10 and the PSD array 600 that passthrough the CPC 140.

The device-side I/O device interconnect controller 500 is disposedbetween the CPC 140 and the PSD array 600 to be the interface and bufferbetween the SVC 100 and the PSD array 600. The device-side I/O deviceinterconnect controller 500 receives the I/O requests and the relateddata transmitted from the CPC 140 and maps and/or transmits them to thePSD array 600.

The CPC 140 includes a CPU chipset 144 that has a parity engine 160, acentral processing unit (CPU) 142, a read only memory (ROM) 146, and anon-volatile random access memory (NVRAM) 148. The CPU 142 can be, forexample, a Power PC CPU. The ROM 146 can be a flash memory for storingthe basic input/output system (BIOS) and/or other programs. The CPU 142is coupled via the CPU chipset 144 to other electronic devices (e.g.,the memory 180). The NVRAM 148 is used to store information related tothe status of I/O operations on the PSD array 600, so that theinformation can be used as a check when the power is unexpectedly shutdown before the I/O operations are finished. The ROM 146, the NVRAM 148,an LCD module 550, and an enclosure management service (EMS) circuit 560are coupled to the CPU chipset 144 via an X-bus. Moreover, the NVRAM 148is optional; namely, it may be omitted in other embodiment. Although theCPU chipset 144 is described as a functional block integrated with theparity engine 160, they can be disposed separately on different chips inpractice.

In an embodiment of the invention, the target data processed in themultiplication operations may come from the PSD array 600 or the host10. The multiplication result may be stored in the memory 180, the diskdrives of the PSD 600, or the buffer built in the parity engine 160 orthe CPU 142 (not shown in the drawing). The algorithm of the inventionis implemented by program coding. The program can be stored in the ROM146 or the memory 180 for the CPC 140 to execute. In other words, theCPC 140 is responsible for generating map tables corresponding to thenumbers in a field domain (e.g., GF(2⁸)) during power on or on line. Thegenerated map tables can be stored in the memory 180. In anotherembodiment of the invention, all the necessary map tables can becomputed in advance and stored in the ROM 146 or the memory 180 so thatthe CPC 140 only needs to access the stored map tables after power on.During the online real-time operations, for a given multiplication unit,an XOR operation unit is taken as an unit to perform an XOR operation onthe target data stored in the memory according to the map tables. Themultiplication result is then obtained after several the XOR operations.

Although in the above embodiment, disks are taken as an example for thephysical storage devices (PSDs) used in the RAID subsystem, it is notedthat other kinds of physical storage devices, such as CD, DVD, etc., canbe used alternatively, depending on different demands of the market.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A method for processing data multiplication in aPSD array, comprising the steps of: providing at least one memory fortemporarily storing target data provided by a data source; providing acentral processing circuit (CPC), generating or accessing at least onemap table each associated with one value in a field, and storing the atleast one map table in the at least one memory, wherein said at leastone map table has a dimension of “a” by “a”, and “a” is a positiveinteger larger than one; defining an XOR operation unit as a length ofdata of “w” bits for performing an XOR operation such that the datalength of the XOR operation unit is “w” bits, wherein “w” is a positiveinteger larger than one; defining a multiplication unit as a length ofdata consisting of “a” XOR operation units for performing amultiplication operation such that the data length of the multiplicationunit is “a” multiplying “w” bits, said target data being of a length ofthe multiplication unit and containing “a” XOR operation units;performing a multiplication operation on the target data to obtain amultiplication result, comprising performing a plurality of XORoperations on the target data according to the at least one map table,wherein each of the plurality of XOR operations is performed on a partof the target data, said part of the target data being data in one ofthe “a” XOR operation units; and storing the multiplication result inthe at least one memory; wherein the plurality of XOR operations areperformed by a hardware computation device; and wherein the length ofthe XOR operation unit “w” bits is independent of “a”.
 2. The method ofclaim 1, wherein a plurality of the multiplication results are furthercomputed by the plurality of XOR operations to obtain a parity or a userdata set.
 3. The method of claim 2, wherein the parity is obtained usingthe following formula:Q=g ⁰ ·D ₀ +g ¹ ·D ₁ +g ² ·D ₂ + . . . g ^(n-1) ·D _(n-1) where g is agenerator of a Galois Field and given to be 2; D₀, D₁, D₂, . . . ,D_(n-1) denote user data series of n number of user data PSDs,respectively; “+” represents an XOR operation; and “·” represents themultiplication operation of the Galois Field.
 4. The method of claim 1,wherein the user data set is obtained using the following formula:D _(x) =A·(P+P _(xy))+B·(Q+Q _(xy))D _(y)=(P+P _(xy))+D _(x) where x and y are the serial numbers of twodata PSDs with errors; D_(x) and D_(y) are user data corresponding tothe two data PSDs x and y; A and B are constants only dependent upon xand y:A=g ^(y-x)·(g ^(y-x)+1)⁻¹B=g ^(−x)(g ^(y-x)+1)⁻¹ P_(xy) and Q_(xy) are the values of P and Q,respectively, when D_(x) and D_(y) are both 0, i.e.,P _(xy) +D _(x) +D _(y) =PQ _(xy) +g ^(x) ·D _(x) +g ^(y) ·D _(y) =Q where “+” represents an XORoperation; and “·” represents the multiplication operation of the GaloisField.
 5. The method of claim 1, wherein the field is a Galois Field andwherein the map table is generated according to an algorithmic rule ofthe Galois Field.
 6. The method of claim 5, wherein when the domain ofthe Galois Field is GF(2⁸) the algorithmic rule is:m′ _(0,j) =m _(7,j), 0≦j≦7m′ _(1,j) =m _(0,j), 0≦j≦7m′ _(2,j) =m _(0,j), 0≦j≦7m′ _(3,j) =m _(2,j) +m _(7,j), 0≦j≦7m′ _(4,j) =m _(3,j) +m _(7,j), 0≦j≦7m′ _(5,j) =m _(4,j), 0≦j≦7m′ _(6,j) =m _(5,j), 0≦j≦7m′ _(7,j) =m _(6,j), 0≦j≦7 where m_(0,j)˜m_(7,j) and m′_(0,j)˜m′_(7,j)with 0≦j≦7 are elements of matrixes M_(K) and M_(K′), respectively,M_(K) being a given matrix associated with K, M_(K′) being a matrixassociated with K′=2·K wherein K≠0.
 7. The method of claim 1, whereinthe plurality of XOR operations are performed according to the followingformula: $Y = {\begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\\vdots \\y_{a - 1}\end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix}m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,7} \\m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,7} \\m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,7} \\\vdots & \vdots & \vdots & \; & \vdots \\m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},7}\end{bmatrix}_{K} \cdot \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\\vdots \\x_{a - 1}\end{bmatrix}}}}$ namely,$y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{ij} \cdot x_{j}} \right)}$where M_(K) is a matrix representing the map table associated with K;m_(i,j) represent elements in the matrix M_(K) with 0≦i, j≦a−1, andm _(i,j) ·x _(j) =x _(j), if m _(i,j)=1m _(i,j) ·x _(j)=0, if m _(i,j)=0 where x₀, x₁, x₂, . . . , and x_(a-1)represent data whose length is the same as the length of the XORoperation unit, respectively, X represents data of the multiplicationunit; and Y represents the result of multiplying K by X.
 8. The methodof claim 6, wherein the XOR operation performed according to the maptables is the one selecting the data of the XOR operation unit whosecorresponding elements in the same row of the matrix M are 1 to do theXOR operation.
 9. The method of claim 1, wherein the length of the XORoperation unit is determined according to a processing unit of thecentral processing unit (CPU) or the hardware computation device. 10.The method of claim 1, wherein the length of the XOR operation unit is32 bits or 64 bits.
 11. The method of claim 1, wherein the length of themultiplication unit is 32 bytes or 64 bytes.
 12. The method of claim 1,wherein the data source is a physical storage device (PSD) array or acomputer host.
 13. A controller for processing data multiplication in aPSD array, comprising: at least one memory for temporarily storingtarget data provided by a data source; and a central processing circuit(CPC) for interacting with the at least one memory, for generating oraccessing at least one map table each associated with one value in afield, and storing the at least one map table in the at least onememory; wherein the CPC is for defining an XOR operation unit as alength of data of “w” bits for performing an XOR operation such that thedata length of the XOR operation unit is “w” bits, wherein “w” is apositive integer larger than one; wherein the CPC is for defining amultiplication unit as a length of data consisting of “a” XOR operationunits for performing a multiplication operation such that the datalength of the multiplication unit is “a” multiplying “w” bits, saidtarget data being of a length of the multiplication unit and containing“a” XOR operation units; wherein the CPC is for performing amultiplication operation on the target data to obtain a multiplicationresult, comprising performing a plurality of XOR operations on thetarget data according to the at least one map table, wherein each of theplurality of XOR operations is performed on a part of the target data,said part of the target data being data in one of the “a” XOR operationunits; wherein the plurality of XOR operations are performed by ahardware computation device; and wherein the length of the XOR operationunit “w” bits is independent of “a”.
 14. The controller of claim 13,wherein the CPC further includes a CPU.
 15. The controller of claim 13,wherein the data source is a PSD array or a computer host for providingthe target data for the multiplication operation.
 16. The controller ofclaim 13 further comprising a device-side I/O device interconnectcontroller connected between the PSD array and the CPC.
 17. Thecontroller of claim 13 further comprising a host-side I/O deviceinterconnect controller connected between the host and the CPC.
 18. Thecontroller of claim 13, wherein the field is a Galois Field and the maptable is generated according to an algorithmic rule of the Galois Field.19. The controller of claim 18, wherein when the domain of the GaloisField is GF(2⁸), the algorithmic rule is:m′ _(0,j) =m _(7,j), 0≦j≦7m′ _(1,j) =m _(0,j), 0≦j≦7m′ _(2,j) =m _(1,j) +m _(7,j), 0≦j≦7m′ _(3,j) =m _(2,j) +m _(7,j), 0≦j≦7m′ _(0,j) =m _(3,j) +m _(7,j), 0≦j≦7m′ _(5,j) =m _(4,j), 0≦j≦7m′ _(6,j) =m _(5,j), 0≦j≦7m′ _(7,j) =m _(6,j), 0≦j≦7 where m_(0,j)˜m_(7,j) and m′_(0,j)˜m′_(7,j)with 0≦j≦7 are elements of matrixes M_(K) and M_(K′), respectively,M_(K) being a given matrix associated with K, M_(K′) being a matrixassociated with K′=2·K wherein K≠0.
 20. The controller of claim 13,wherein the plurality of XOR operations are performed according to thefollowing formula: $Y = {\begin{bmatrix}y_{0} \\y_{1} \\y_{2} \\\vdots \\y_{a - 1}\end{bmatrix} = {{M_{K} \cdot X} = {\begin{bmatrix}m_{0,0} & m_{0,1} & m_{0,2} & \ldots & m_{0,7} \\m_{1,0} & m_{1,1} & m_{1,2} & \ldots & m_{1,7} \\m_{2,0} & m_{2,1} & m_{2,2} & \ldots & m_{2,7} \\\vdots & \vdots & \vdots & \; & \vdots \\m_{{a - 1},0} & m_{{a - 1},1} & m_{{a - 1},2} & \ldots & m_{{a - 1},7}\end{bmatrix}_{K} \cdot \begin{bmatrix}x_{0} \\x_{1} \\x_{2} \\\vdots \\x_{a - 1}\end{bmatrix}}}}$ namely,$y_{i} = {\sum\limits_{j = 0}^{a - 1}\left( {m_{ij} \cdot x_{j}} \right)}$where M_(K) is a matrix representing the map table associated with K;m_(i,j) represent elements in the matrix M_(K) with 0≦i, j≦a−1, andm _(i,j) ·x _(j) =x _(j), if m _(i,j)=1m _(i,j) ·x _(j)=0, if m _(i,j)=0 where x₀, x₁, x₂, . . . , and x_(a-1)represent data whose length is the same as the length of the XORoperation unit, respectively, X represents data of the multiplicationunit; and Y represents the result of multiplying K by X.
 21. Thecontroller of claim 13, wherein the length of the XOR operation unit isdetermined according to a processing unit of the central processing unit(CPU) or the hardware computation device.
 22. The controller of claim13, wherein the length of the XOR operation unit is 32 bits or 64 bits.23. The controller of claim 13, wherein the length of the multiplicationunit is 32 bytes or 64 bytes.
 24. A method for processing datamultiplication in a PSD array for computing the product of a number Kand a data series X, comprising the steps of: providing at least onememory for temporarily storing target data provided by a data source;providing a central processing circuit (CPC) and generating or accessinga map table associated with the number K, and storing the map table inthe at least one memory; defining an XOR operation unit as a length ofdata of “w” bits for performing an XOR operation such that the datalength of the XOR operation unit is “w” bits, wherein “w” is a positiveinteger larger than one; defining a multiplication unit as a length ofdata consisting of “a” XOR operation units for performing amultiplication operation such that the data length of the multiplicationunit is “a” multiplying “w” bits, said target data being of a length ofthe multiplication unit and containing “a” XOR operation units;performing a multiplication operation on each of the target data of thedata series X, comprising performing a plurality of XOR operations onthe target data according to the map table, wherein each of theplurality of XOR operations is performed on a part of the target data,said part of the target data being data in one of the “a” XOR operationunits; and obtaining a multiplication result of the number K with thedata series X when all the multiplication operations are finished, andstoring the multiplication result in the at least one memory; whereinthe plurality of XOR operations are performed by a hardware computationdevice; and wherein the length of the XOR operation unit “w” bits isindependent of “a”.